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Exam Prep  ·  WRES1201  ·  Single-File  ·  2026

CSA Study App

A self-contained exam prep tool for WRES1201 (Computer Systems Architecture). Topic guide, formula reference, MCQ drills, and interactive visualizers for cache mapping, Hamming codes, and arithmetic shifts, with every number re-randomized on each reload so it never gets stale.

Vanilla JS Single HTML File Procedural Question Generation Lucide Icons Cloudflare Pages
Status
Completed · Live
Year
2026
Type
Study Tool · Course Prep
File Size
1 HTML file
01 Project Overview

CSA Study App was built during finals week for WRES1201, Computer Systems Architecture, after I realized the questions I actually needed practice on (instruction mix, CPI, cache addressing, Hamming codes, disk timing) weren't well covered by any existing revision material.

Same constraint as RafiFinance: one HTML file, no dependencies beyond a CDN icon set. Every numeric question — instruction counts, clock rates, cache sizes, RPMs — is generated with randomised values each page load, so practising twice never means memorising the same answer.

Built to be shared, not just used. Once it worked for me, I put it on its own subdomain and sent it to classmates, no install, no signup, just open the link and start drilling.

Covers T1 through T10 of the syllabus, with topics outside the final exam scope (T1, T7, T9) clearly tagged so revision time goes where it actually counts.

02 Features
Topic Guide (T1–T10)
Every topic explained, what it is, why it matters, key concepts, and exam focus, with non-final topics tagged so you don't waste time on them.
Formula Reference
Every formula in the syllabus, when to use it, what each variable means, and a worked example with real numbers.
Challenge Drills
Theory and applied questions across every topic. Numbers and answer order re-roll on every refresh, so the same question never looks identical twice.
MCQ Concept Drill
Multiple-choice theory + applied questions with options that shuffle on every reload, built so you can't pattern-match the answer position.
Shift Visualizer
Interactive bit-shift visualization for logical/arithmetic shifts, see exactly which bits move where and what falls off the end.
Hamming Code Tool
Generates a random data word, walks through parity-bit placement and the even-parity XOR calculation for each position step by step.
Cache Mapper
Splits a binary memory address into tag, line, and offset for direct-mapped / set-associative caches, with the bit math shown explicitly.
Smart Calculator
Enter whatever the question already gives you, CPI, clock rate, instruction count, disk RPM, and get every derived value at once, no need to remember which formula comes first.
03 Topics Covered

The syllabus spans ten topic blocks. Topics tagged not-in-final are kept in the app for completeness but hidden by default with a "Focus Mode" toggle:

T2: Performance Metrics
Instruction mix, CPI, clock cycles, MIPS, execution time, speedup, the cluster of formulas that show up in nearly every exam question.
T3: Bus & Data Transfer
Transfer rate from bus width, clock speed, and bus cycles, with the bit-to-byte conversion that trips most people up.
T4: Cache Memory
Address splitting (tag / line / offset), cache sizing, line and set counts, and miss-time calculation.
T5: Error Correction
Hamming code parity-bit calculation using even-parity XOR across covered bit positions.
T6: Secondary Storage
Seek time, rotational latency, transfer time per sector, disk capacity, and RAID 0/1/3/4/5/6 capacity multipliers.
T8: Instruction Sets
Addressing modes and instruction format rules, drilled as randomized name-the-rule questions.
T10: Pipelining
Pipelined execution time, fill/drain cycles, and per-stage time with latch overhead included.
T1, T7, T9: Not in Final
Kept in the app and tagged accordingly, but hidden by default in Focus Mode so revision stays scoped to what's actually examined.
04 Why Randomized Numbers

Most revision PDFs reuse the same five worked examples everyone has already memorised. Generating the values at runtime means the formula gets tested, not the specific numbers.

The drill never repeats. Closing the tab and reopening it gives a fresh set of values for every question type, you can practice the same topic dozens of times without the answer becoming familiar by memory instead of method.

The MCQ section goes a step further: answer order shuffles independently of the question values, so guessing by position never works either.

4b Under the Hood, The Hard Math

The "By the Numbers" tiles hide a lot of formula work. This section unpacks the heavier derivations the app evaluates live, the ones students most often get wrong because they collapse several conversions into one step. Every quantity below is recomputed on each page load against freshly randomized inputs.

1. CPU performance, from instruction mix to wall-clock time. Given an instruction mix where class i occurs with frequency f_i and costs c_i cycles, the effective cycles-per-instruction is the frequency-weighted mean, and execution time folds in the clock period:

Effective CPI & execution time
\text{CPI}_{\text{eff}} = \sum_{i=1}^{n} f_i\, c_i, \qquad T_{\text{exec}} = \frac{I \times \text{CPI}_{\text{eff}}}{f_{\text{clk}}} = I \times \text{CPI}_{\text{eff}} \times t_{\text{cycle}}
Itotal instruction count (dynamic, not static)
f_i, c_irelative frequency and cycle cost of instruction class i, with \sum f_i = 1
f_clkclock frequency in Hz; t_cycle = 1/f_clk

From here MIPS is a derived rate, \text{MIPS} = \dfrac{f_{\text{clk}}}{\text{CPI}_{\text{eff}} \times 10^{6}}, which is exactly where unit errors creep in, the 10^{6} is per million instructions, not the SI mega-prefix on the clock.

2. Amdahl's Law, the ceiling on speedup. When only a fraction p of a workload is accelerated by a factor s, the overall speedup is bounded, and the bound is brutal:

Speedup with a hard asymptote
S(s) = \frac{1}{(1-p) + \dfrac{p}{s}} \quad\xrightarrow[s\to\infty]{}\quad S_{\max} = \frac{1}{1-p}

The app uses this to make a point students miss: if p = 0.9, no amount of hardware ever beats a 10\times speedup, because the serial 10\% dominates in the limit.

3. Pipelining, throughput vs. latency with latch overhead. A k-stage pipeline does not divide time by k. The clock is pinned to the slowest stage plus register-latch delay, and the pipe must fill before the first result emerges. For N instructions:

Cycle time, total time, and limiting speedup
\tau = \max_j(\tau_j) + \tau_{\text{latch}}, \qquad T_{\text{pipe}} = \big(k + (N-1)\big)\,\tau, \qquad S = \frac{N \cdot k\,\tau_{\text{unpipe}}}{\big(k+N-1\big)\tau} \xrightarrow[N\to\infty]{} k
Why the ideal is never reached. The (k-1) fill cycles and the per-stage latch delay \tau_{\text{latch}} both tax throughput, so realized speedup sits strictly below the k\times asymptote for any finite instruction stream.

4. Cache address arithmetic, derived bitfields, not guessed. For a 2^m-byte address space, block size B = 2^b bytes, and a set-associative cache holding S = 2^s sets, the address splits into three exact bitfields:

Tag / index / offset partition
\underbrace{m - s - b}_{\text{tag bits}} \;\Vert\; \underbrace{s}_{\text{index bits}} \;\Vert\; \underbrace{b}_{\text{offset bits}}, \qquad S = \frac{C}{B \times A}

where C is total cache capacity and A is associativity. Average memory access time then composes the hierarchy recursively:

AMAT
\text{AMAT} = t_{\text{hit}} + m_{\text{rate}} \times t_{\text{penalty}}

5. Hamming SEC code, the parity inequality. To correct any single-bit error over d data bits, the number of parity bits r must satisfy the redundancy inequality, because the r check bits must address every one of the d+r code positions plus the no-error syndrome:

Minimum parity bits
2^{r} \;\geq\; d + r + 1

Each parity bit p_k (sitting at position 2^{k}) covers exactly the positions whose binary index has bit k set, and is fixed by even parity:

Even-parity assignment via XOR
p_k = \bigoplus_{\substack{j\,:\,\lfloor j/2^{k}\rfloor \bmod 2 = 1}} b_j

On read, the syndrome \mathbf{s} = H\mathbf{r}^{\mathsf{T}} is the XOR of all parity checks; if non-zero, its value read as a binary number is the 1-indexed position of the flipped bit, which is why the app can point straight at the error.

6. Disk access time, three independent latencies plus capacity. A single sector read is the sum of seek, half-a-rotation average rotational latency, and transfer time; rotational figures come from RPM, so a unit conversion is unavoidable:

Average rotational latency is half the rotation period, derived from revolutions per minute:
t_{\text{rot}} = \frac{1}{2}\cdot\frac{60}{\text{RPM}}\ \text{seconds}
Transfer time for one sector is its fraction of a full track, read in one rotation:
t_{\text{xfer}} = \frac{1}{\text{sectors per track}}\cdot\frac{60}{\text{RPM}}
Total access time and raw capacity then assemble cleanly:
t_{\text{access}} = t_{\text{seek}} + t_{\text{rot}} + t_{\text{xfer}}, \quad \text{Cap} = \text{surfaces}\times\text{tracks}\times\text{sectors}\times\text{bytes}_{\text{sector}}

RAID then applies a usable-capacity multiplier on top: N\!-\!1 drives of N for RAID 5, N\!-\!2 for RAID 6, and N/2 for mirrored RAID 1.

05 Built for Sharing
One Link, No Install
Just open csastudy.rafiarsya.com, no account, no app store, works on any phone or laptop with a browser.
Shared with Classmates
Built originally for personal revision, then handed off to coursemates for WRES1201 finals prep.
No Data Collected
No login, no analytics dashboard, no stored answers, just open it and drill.
Exam-Scoped
Focus Mode hides non-final topics so study time goes straight to what's actually tested.
App Sections
Topic Guide100%
Formula Reference100%
Challenge Drills100%
MCQ Concept Drill100%
Shift Visualizer100%
Hamming Code Tool100%
Cache Mapper100%
Smart Calculator100%
Tech Stack
Vanilla JS HTML5 CSS3 Procedural Generation Lucide Icons CDN Cloudflare Pages
One file. Full exam prep kit.
No signup, no install. Open the link, pick a topic, and the numbers are different every time you come back.
Open CSA Study App